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semiconductor group 121 ? 8 388 608 words by 8-bit organization ? 0 to 70 ?c operating temperature ? fast access and cycle time ras access time: 50 ns (-50 version) 60 ns (-60 version) cycle time: 90 ns (-50 version) 110 ns (-60 version) cas access time: 13 ns ( -50 version) 15 ns ( -60 version) ? fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) ? single + 3.3 v ( 0.3v) power supply ? low power dissipation max. 396 active mw ( hyb 3164800j/t-50) max. 360 active mw ( hyb 3164800j/t-60) max. 504 active mw ( hyb 3165800j/t-50) max. 432 active mw ( hyb 3165800j/t-60) 7.2 mw standby (ttl) 720 w standby (mos) ? read, write, read-modify-write, cas-before- ras refresh (cbr), ras-only refresh, hidden refresh and self refresh modes ? fast page mode capability ? 8192 refresh cycles/128 ms , 13 r/ 10c addresses (hyb 3164800j/t) ? 4096 refresh cycles/ 64 ms , 12 r/ 11c addresses (hyb 3165800j/t) ? plastic package: p-soj-34-1 500 mil hyb 3164(5)800j p-tsopii-34-1 500 mil hyb 3164(5)800t 8m x 8-bit dynamic ram preliminary information hyb 3164800j/t -50/-60 hyb 3165800j/t -50/-60 (4k & 8k refresh)
semiconductor group 122 hyb 3164(5)800j/t-50/-60 8m x 8-dram this device is a 64 mbit dynamic ram organized 8 388 608 by 8 bits. the device is fabricated in siemens/ibms most advanced first generation 64mbit cmos silicon gate process technology. the circuit and process design allow this device to achieve high performance and low power dissipation. this dram operates with a single 3.3 +/-0.3v power supply and interfaces with either lvttl or lvcmos levels. multiplexed address inputs permit the hyb 3164(5)800j/t to be packaged in a 500 mil wide soj-34 or tsop-34 plastic package. these packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. ordering information pin names type ordering code package descriptions hyb 3164800j-50 on request p-soj-34-1 500 mil dram (access time 50 ns) hyb 3164800j-60 on request p-soj-34-1 500 mil dram (access time 60 ns) hyb 3164800t-50 on request p-tsopii-34-1 500 mil dram (access time 50 ns) hyb 3164800t-60 on request p-tsopii-34-1 500 mil dram (access time 60 ns) hyb 3165800j-50 on request p-soj-34-1 500 mil dram (access time 50 ns) hyb 3165800j-60 on request p-soj-34-1 500 mil dram (access time 60 ns) hyb 3165800t-50 on request p-tsopii-34-1 500 mil dram (access time 50 ns) hyb 3165800t-60 on request p-tsopii-34-1 500 mil dram (access time 60 ns) a0-a12 address inputs for hyb 3164800j/t a0-a11 address inputs for hyb 3165800j/t ras row address strobe oe output enable i/o1-i/o8 data input/output cas column address strobe write read/write input vcc power supply ( + 3.3v) vss ground
semiconductor group 123 hyb 3164(5)800j/t-50/-60 8m x 8-dram pin configuration p-soj-34-1 (500 mil) p-tsopii-34-1 (500 mil)
semiconductor group 124 hyb 3164(5)800j/t-50/-60 8m x 8-dram truth table function ras cas write oe row addr col addr i/o1- i/o8 standby h h - x x x x x high impedance read l l h l row col data out early-write l l l x row col data in delayed-write l l h - l h row col data in read-modify-write l l h - l l - h row col data out, data in fast page mode read 1st cycle l h - l h l row col data out 2nd cycle l h - l h l n/a col data out fast page mode early write 1st cycle l h - l l x row col data in 2nd cycle l h - l l x n/a col data in fast page mode rmw 1st cycle l h - l h - l l - h row col data out, data in 2st cycle l h - l h - l l - h n/a col data out, data in ras only refresh l h x x row n/a high impedance cas-before-ras refresh h - l l h x x n/a high impedance test mode entry h - l l l x x n/a high impedance hidden refresh read l-h-l l h l row col data out write l-h-l l l x row col data in
semiconductor group 125 hyb 3164(5)800j/t-50/-60 8m x 8-dram block diagram for hyb 3165800j/t
semiconductor group 126 hyb 3164(5)800j/t-50/-60 8m x 8-dram block diagram for hyb 3164800j/t
semiconductor group 127 hyb 3164(5)800j/t-50/-60 8m x 8-dram absolute maximum ratings operating temperature range..............................................................................................0 to 7 0 ?c storage temperature range.........................................................................................C 55 to 150 ? c input/output voltage..................................................................................-0.5 to min (vcc+0.5,4.6) v power supply voltage....................................................................................................-0.5v t o 4.6 v power dissipation.............................................................................................................. ........1.0 w data out current (short circuit)............................................................................................... ...50 ma note stresses above those listed under ?absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may effect device reliability. dc characteristics t a = 0 to 70 ?c, v ss = 0 v, v cc = 3.3 v 0.3 v, (values in brackets for hyb 3165800j/t) parameter symbol limit values unit note min. max. input high voltage v ih 2.0 vcc+0.3 v 1) input low voltage v il C 0.3 0.8 v 1) output high voltage (lvttl) output ?h level voltage (iout = -2ma) v oh 2.4 C v output low voltage (lvttl) output ?llevel voltage (iout = +2ma) v ol C 0.4 v output high voltage (lvcmos) output ?h level voltage (iout = -100ua) v oh vcc-0.2 - v ouput low voltage (lvcmos) output ?l level voltage (iout = +100ua) v ol - 0.2 v input leakage current,any input (0 v < vin < vcc , all other pins = 0 v i i(l) C 2 2 m a output leakage current (do is disabled, 0 v < vout < vcc ) i o(l) C 2 2 m a average vcc supply current: -50 ns version -60 ns version ( ras, cas, address cycling: trc = trc min.) i cc1 C C 110 (140) 100 (120) ma ma 2) 3) 4) standby vcc supply current ( ras= cas= vih) i cc2 C 2 ma C
semiconductor group 128 hyb 3164(5)800j/t-50/-60 8m x 8-dram average vcc supply current, during ras-only refresh cycles: -50 ns version -60 ns version (ras cycling: cas = vih: trc = trc min.) i cc3 C C 110 (140) 100 (120) ma ma 2) 4) average vcc supply current, during fast page mode: -50 ns version -60 ns version ( ras = v il , cas, address cycling: tpc=tpc min.) i cc4 C C 85 (85) 75 (75) ma ma 2) 3) 4) standby vcc supply current ( ras= cas= vcc-0.2v) i cc5 C 200 a C average vcc supply current, during cas-before- ras refresh mode: -50 ns version -60 ns version ( ras, cas cycling: trc = trc min.) i cc6 C C 110 (140) 100 (120) ma ma 2) 4) self refresh current average power supply current during self refresh. (cbr cycle with tras>trassmin, cas held low, we = vcc-0.2v, address and din=vcc-0.2v or 0.2v) i cc7 C 400 a capacitance t a = 0 to 70 ?c, v cc = 3.3 v 0.3 v, f = 1 mhz parameter symbol limit values unit min. max. input capacitance (a0 to a11,a12) c i1 C5pf input capacitance ( ras, cas, write, oe) c i2 C7pf i/o capacitance (i/o1-i/o8) c io C7pf dc characteristics (contd) t a = 0 to 70 ?c, v ss = 0 v, v cc = 3.3 v 0.3 v, (values in brackets for hyb 3165800j/t) parameter symbol limit values unit note min. max.
semiconductor group 129 hyb 3164(5)800j/t-50/-60 8m x 8-dram ac characteristics (note: 6,7,8) t a = 0 to 70 ?c, v cc = 3.3 0.3v parameter symbol hyb 3164(5)800 j/t-50 hyb 3164(5)800 j/t-60 unit note min. max. min. max. common parameters random read or write cycle time t rc 90 C 110 C ns ras precharge time t rp 30 C 40 C ns ras pulse width t ras 50 100k 60 100k ns cas pulse width t cas 13 100k 15 100k ns row address setup time t asr 0C0Cns row address hold time t rah 8C10Cns column address setup time t asc 0C0Cns column address hold time t cah 10 C 10 C ns ras to cas delay time t rcd 18 37 20 45 ras to column address delay time t rad 13 25 15 30 ns ras hold time t rsh 13 C 15 C ns cas hold time t csh 50 C 60 C ns cas to ras precharge time t crp 5C5Cns transition time (rise and fall) t t 3 30 3 30 ns 7 refresh period for hyb3164800 t ref C 128 C 128 ms refresh period for hyb3165800 t ref C 64 C 64 ms read cycle access time from ras t rac C 50 C 60 ns 8, 9 access time from cas t cac C 13 C 15 ns 8, 9 access time from column address t aa C 25 C 30 ns 8, 10 oe access time t oea C 13 C 15 ns 8 column address to ras lead time t ral 25 C 30 C ns read command setup time t rcs 0C0Cns read command hold time t rch 0C0Cns 11 read command hold time referenced to ras t rrh 0C0Cns 11
semiconductor group 130 hyb 3164(5)800j/t-50/-60 8m x 8-dram cas to output in low-z t clz 0C0Cns 8 output buffer turn-off delay t off C 13 C 15 ns 12 output buffer turn-off delay from oe t oez C 13 C 15 ns 12 data to oe low delay t dzo 0C0Cns 13 cas high to data delay t cdd 13 C 15 C ns 14 oe high to data delay t odd 13 C 15 C ns 14 write cycle write command hold time t wch 8C10Cns write command pulse width t wp 8C10Cns write command setup time t wcs 0C0Cns 15 write command to ras lead time t rwl 13 C 15 C ns write command to cas lead time t cwl 13 C 15 C ns data setup time t ds 0C0Cns 16 data hold time t dh 10 C 10 C ns 16 cas delay time from din t dzc 0C0Cns 13 read-modify-write cycle read-write cycle time t rwc 126 C 150 C ns ras to we delay time t rwd 68 C 80 C ns 15 cas to we delay time t cwd 31 C 35 C ns 15 column address to we delay time t awd 43 C 50 C ns 15 oe command hold time t oeh 13 C 15 C ns fast page mode cycle fast page mode cycle time t pc 35 C 40 C ns cas precharge time t cp 10 C 10 C ns access time from cas precharge t cpa C 30 C 35 ns 8 ras pulse width t ras 50 200k 60 200k ns ac characteristics (contd) (note: 6,7,8) t a = 0 to 70 ?c, v cc = 3.3 0.3v parameter symbol hyb 3164(5)800 j/t-50 hyb 3164(5)800 j/t-60 unit note min. max. min. max.
semiconductor group 131 hyb 3164(5)800j/t-50/-60 8m x 8-dram cas precharge to ras delay t rhcp 30 C 35 C ns fast page mode read-modify-write cycle fast page mode read-write cycle time t prwc 71 C 80 C ns cas precharge to we t cpwd 48 C 55 C ns cas-before- ras refresh cycle cas setup time t csr 5C5Cns cas hold time t chr 10 C 10 C ns ras to cas precharge time t rpc 5C5Cns write to ras precharge time t wrp 10 C 10 C ns write hold time referenced to ras t wrh 10 C 10 C ns cas-before- ras counter test cycle cas precharge time t cpt 25 C 30 C ns test mode cycle write command setup time t wts 10 C 10 C ns write command hold time t wth 10 C 10 C ns self refresh cycle ras pulse width t rass 100k C 100k C ns 17 ras precharge time t rps 90 C 110 C 17 cas hold time t chs -50 C -50 C ns 17 ac characteristics (contd) (note: 6,7,8) t a = 0 to 70 ?c, v cc = 3.3 0.3v parameter symbol hyb 3164(5)800 j/t-50 hyb 3164(5)800 j/t-60 unit note min. max. min. max.
semiconductor group 132 hyb 3164(5)800j/t-50/-60 8m x 8-dram notes: 1) all voltages are referenced to vss. 2) icc1, icc3, icc4 and icc6 and icc7 depend on cycle rate. 3) icc1 and icc4 depend on output loading. specified values are measured with the output open. 4) address can be changed once or less while ras = vil.in the case of icc4 it can be changed once or less during a fast page mode cycle ( tpc). 5) an initial pause of 100 s is required after power-up followed by 8 ras-only-refresh cycles, before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas-before- ras initialization cycles instead of 8 ras cycles are required. 6) ac measurements assume tt = 5 ns. 7) vih (min.) and vil (max.) are reference levels for measuring timing of input signals. also, transition times are measured between vih and vil. 8) measured with the specified current load and 100 pf at voh = 2.0 v and vol = 0.8 v. 9) operation within the trcd (max.) limit ensures that trac (max.) can be met. trcd (max.) is specified as a reference point only: if trcd is greater than the specified trcd (max.) limit, then access time is controlled by tcac. 10) operation within the trad (max.) limit ensures that trac (max.) can be met. trad (max.) is specified as a reference point only: if trad is greater than the specified trad (max.) limit, then access time is controlled by taa. 11) either trch or trrh must be satisfied for a read cycle. 12) toff (max.) and toez (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13) either tdzc or tdzo must be satisfied. 14) either tcdd or todd must be satisfied. 15) twcs, trwd, tcwd, tawd and tcpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if twcs > twcs (min.), the cycle is an early write cycle and the i/o pin will remain open-circuit (high impedance) through the entire cycle; if trwd > trwd (min.), tcwd > tcwd (min.), tawd > tawd (min.) and tcpwd > tcpwd (min.) , the cycle is a read-write cycle and i/o pins will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of the i/o pins (at access time) is indeterminate. 16) these parameters are referenced to cas leading edge in early write cycles and to write leading edge in read-modify-write cycles. 17) when using self refresh mode, the following refresh operations must be performed to ensure proper dram operation: if row addresses are being refresh in an evenly distributed manner over the refresh iterval using cbr refresh cycles, then only one cbr cycle must be performed immediatly after exit from self refresh. if row addresses are being refresh in any other manner (ror - distributed/burst or cbr-burst) over the refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey after exit from self refresh
semiconductor group 133 hyb 3164(5)800j/t-50/-60 8m x 8-dram read cycle row address column address row address valid data out ras cas address write oe i/o1-i/o4 (inputs) i/o1-i/o8 (outpus) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rc t csh t rad t cas t rp t rah t crp t rsh t rcd t ral t asr t cah t asc t asr t rch t rrh t rcs t aa t oea t clz t cac t oez t odd t cdd t off t dzc t dzo t rac hi z hi z h or l 8
semiconductor group 134 hyb 3164(5)800j/t-50/-60 8m x 8-dram write cycle (early write) ras cas address write oe i/o1-i/o8 (inputs i/o1-i/o8 (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t rc t csh t rad t cas t rp t crp t rsh t rcd t ral t asr t cah t asr t cwl t rwl t wp t asc t wch valid data in t ds t dh hi z column address address row row address t rah t wcs h or l
semiconductor group 135 hyb 3164(5)800j/t-50/-60 8m x 8-dram write cycle ( oe controlled write) valid data t rwl t wp t oeh t odd t cwl t dzo t oea t clz t ds t oez t dh t rc v ih v il row address t dzc h or l hi-z hi-z column address address row t asc t rad t ral t cah t rah ras cas address write oe i/o1-i/o8 (inputs) i/o1-i/o8 (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t csh t cas t rp t crp t rsh t rcd t asr t asr
semiconductor group 136 hyb 3164(5)800j/t-50/-60 8m x 8-dram read-write (read-modify-write) cycle row address row address t csh t cas t crp t rwc t awd t asr t rp t ras t rah t cah i/o1-i/o8 (outputs) v oh v ol v ih v il v ih v il i/o1-i/o8 (inputs) oe write v ih v il t asr column address t rcd t dh t rsh t rad t cwd t oeh t rwd t rwl t cwl t clz t wp t rcs t aa t oea t ds t dzc t dzo t odd t cac t oez valid data in data out t rac h or l t asc v ih v il v ih v il ras cas address v ih v il
semiconductor group 137 hyb 3164(5)800j/t-50/-60 8m x 8-dram fast page mode read-modify-write cycle t cah t cp t dzc t dzo t rac t cac t clz t rcs t aa t oea t rcd t rad t rah t asr t asc t cas t cas t prwc t cwd t cah t asc t cas t rsh t rp t crp t asr t cah t asc t ral t cwd t rwd t cwl t cwl t cwd t awd t awd t wp t wp t cwl t rwl t awd t wp t odd t oeh t dh t ds t cpa t oez t clz t dzc t aa t cac t oea t ds t oez t dh t oeh t aa t odd t dzc t cpa t oea t clz t ds t dh t oeh t odd ras v ih v il cas v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol write oe address (inputs) (outputs) data in data in data in data out out data data out address row column address address column address row address t rasp t csh column t cpwd t cpwd h or l i/o1-i/o8 i/o1-i/o8
semiconductor group 138 hyb 3164(5)800j/t-50/-60 8m x 8-dram fast page mode read cycle t rasp t cas t cas t pc t cp t rcd t csh t cah t cah t asc t asc t asr t rah t rad t rcs t rcs t rcs t asc t cah t cas t rsh t crp t rp t asr t rch t cpa t oea t oea t aa t aa t dzc t dzc t cdd t rrh t cpa t oea t aa t dzc t dzo t odd t odd t dzo t odd t dzo t off t oez t oez t off t oez t cac t cac t clz t clz t clz t off t off t cac valid data out data out data out valid valid column address address addr address column row row ras i/o1-i/o8 (outputs) i/o1-i/o8 (inputs) oe write address cas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il h or l t rhcp t rch v oh v ol column address
semiconductor group 139 hyb 3164(5)800j/t-50/-60 8m x 8-dram fast page mode early write cycle t rasp t rp t rsh t cas t cas t cp t crp t ral t cah t asr t cwl t rwl t cah t asc t asc t cwl t cwl t wcs t wcs t wcs t wch t wp t wp t wch t wp t wch t rad t cas t rcd t pc t cah t rah t asr t asc t dh t ds t ds t dh t dh t ds column address address address column column row addr valid data in valid valid data in data in column address hi-z ras i/o1-i/o8 (outputs) i/o1-i/o8 (inputs) oe write address cas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il h or l v oh v ol
semiconductor group 140 hyb 3164(5)800j/t-50/-60 8m x 8-dram ras-only refresh cycle t crp t rah t rp t ras t rc t asr t asr t rpc v ih v il v ih v il v ih v il v oh v ol row address row address hi-z address ras cas i/o1-i/o8 (outputs) h or l
semiconductor group 141 hyb 3164(5)800j/t-50/-60 8m x 8-dram cas-before- ras refresh cycle t rp t ras t rp t rc t crp t cp t rpc t chr t wrh t wrp t csr t rpc t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z h or l ras i/o1-i/o8 (outputs) i/o1-i/o8 (inputs) oe write cas v oh v ol
semiconductor group 142 hyb 3164(5)800j/t-50/-60 8m x 8-dram hidden refresh cycle (read) ras i/o1-i/o8 (outputs) i/o1-i/o8 (inputs) oe write address cas t rc t rc t ras t ras t rp t rp t crp t chr t rad t cah t asc t rah t asr t asr t rcs t rrh t aa t dzc t dzo t cac t rac t clz t oez t off t odd t cdd t rcd t rsh t oea v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t wrp t wrh h or l valid data out row address column address row addr hi-z v oh v ol
semiconductor group 143 hyb 3164(5)800j/t-50/-60 8m x 8-dram hidden refresh cycle (early write) ras i/o1-i/o8 (outputs) i/o1-i/o8 (inputs) oe write v ih v il address v ih v il v ih v il v ih v il cas v ih v il v ih v il h or l t rc t ras t rcd t rsh t rad t cah t wcs t wch t wp t asr t rah t ds t dh t asr t crp t chr t rp t ras t rc t rp t asc address row addr row address valid data hi-z column v oh v ol
semiconductor group 144 hyb 3164(5)800j/t-50/-60 8m x 8-dram cas-before- ras refresh counter test cycle t csr t asr t asc t chr t cpt t wrp t ral t cah t rsh t rp t ras t cas t rcs t cdd t cac t aa t wrh t oea t odd t clz t dzc t dzo t oez t off t rwl t cwl t wch t wcs t wrh t wrp t ds t odd t dh t wrh t wrp t oez t rwl t cwl t awd t cwd t wp t rcs t cac t oea t oeh t aa t clz t dh t dzo t ds t dzc t cac v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il i/o1-i/o8 (inputs) ras i/o1-i/o8 (inputs) oe write address cas i/o1-i/o8 (outputs) i/o1-i/o8 (outputs) i/o1-i/o8 (inputs) write oe write oe i/o1-i/o8 (outputs) column address row address data in valid data out valit data in hi-z hi-z hi-z read cycle read-modify-write cycle write cycle t rrh t rch d.out
semiconductor group 145 hyb 3164(5)800j/t-50/-60 8m x 8-dram test mode entry t rc t ras t rp t rpc t crp t chr t wth t rpc t rp t cp t csr t wts t cdd t off t oez t odd i/o1-i/o8 (outputs) v oh v ol v ih v il v ih v il i/o1-i/o8 (inputs) oe write v ih v il cas ras v ih v il v ih v il h or l hi-z adress t rah t asr v ih v il row address
semiconductor group 146 hyb 3164(5)800j/t-50/-60 8m x 8-dram cas-before-ras self refresh t rps t rass t rp t crp t cp t rpc t wrh t wrp t csr t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z h or l ras i/o1-i/o8 (outputs) i/o1-i/o8 (inputs) oe write cas v oh v ol t chs
semiconductor group 147 hyb 3164(5)800j/t-50/-60 8m x 8-dram package outlines p-soj-34-1 (500 mil) (plastic small outline j-leaded package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
semiconductor group 148 hyb 3164(5)800j/t-50/-60 8m x 8-dram p-tsopii-34-1 (500 mil) (plastic thin small outline package type sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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